Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-17
0x480 PCI Express Link Capabilities Update Register
(PEX_LINKCAP_UPDATE)
R/W 0x0000_3D41 14.4.6.10/14-69
0x490 PCI Express Slot Capabilities Update Register
(PEX_SLCAP_UPDATE)
R/W 0x0000_07C0 14.4.6.11/14-71
0x4B0 PCI Express Configuration Ready Register (PEX_CFG_READY) Mixed 0x0000_0000 14.4.6.12/14-71
PCI Express BAR Configuration Registers (EP Mode)
0x4D8 PCI Express BAR Size Low Configuration Register
(PEX_BAR_SIZEL)
R/W 0xFC00_0000 14.4.7.1/14-72
0x4DC Reserved — — —
0x4E0 PCI Express BAR Select Configuration Register
(PEX_BAR_SEL)
R/W 0x0000_0400 14.4.7.2/14-73
0x504 PCI Express BAR Prefetch Configuration Register
(PEX_BAR_PF)
R/W 0x0000_0400 14.4.7.3/14-74
PCI Express Extended Status and Control Register
0x590 PCI Express PME_To_Ack Timeout Register
(PEX_PME_TO_ACK_TOR)
Mixed 0x0019_5460 14.4.8.1/14-74
0x594 PCI Express PME_To_Ack Status Register
(PEX_PME_TO_ACK_SR)
w1c 0x0000_0000 14.4.8.2/14-75
0x5A0 PCI Express PCI Interrupt Mask Register
(PEX_SS_INTR_MASK)
Mixed 0x0000_003F 14.4.8.3/14-76
PCI Express CSB Bridge Registers
Global Registers
0x800–
0x804
Reserved — — —
0x808 PCI Express CSB Bridge Control register (PEX_CSB_CTRL) R/W 0x0000_0130 14.5.2.1/14-78
0x80C Reserved — — —
0x814 PCI Express DMA Descriptor Timer Register
(PEX_DMA_DSTMR)
R/W 0x0000_0000 14.5.2.2/14-79
0x818 Reserved — — —
0x81C PCI Express CSB Bridge Status register (PEX_CSB_STAT) R 0x0000_0000 14.5.2.3/14-79
0x820 Reserved — — —
PCI Express Outbound PIO Registers
0x840 PCI Express Outbound PIO Control Register
(PEX_CSB_OBCTRL)
R/W 0x0000_0000 14.5.3.1/14-80
0x844 PCI Express Outbound PIO Status Register
(PEX_CSB_OBSTAT)
w1c 0x0000_0000 14.5.3.2/14-81
0x848 Reserved — — —
PCI Express Inbound PIO Registers
Table A-20. PCI Express Controller Registers
PCI Express—Block Base Address 0x0_9000
Offset Register Access Reset Section/Page