Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-13
4.3.2.2.1 Boot Memory Space (BMS)
BMS defines the initial value of the e300 core MSR[IP] bit, which specifies the location of the interrupt
vectors (including the hard reset exception vector). The device defines the default boot ROM memory
space to be 8 Mbytes at addresses 0x0000_0000 to 0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF.
When the core comes out of reset, if it is enabled to boot, it fetches boot code from one of two addresses,
0x0000_0100 or 0xFFF0_0100, and exceptions are vectored to the physical addresses, 0x000n_nnnn or
0xFFFn_nnnn appropriately. This bit specifies whether an interrupt vector offset is prepended with 0xFFF
or 0x000. In the description below, n_nnnn is the offset of the exception vector.
The boot memory space reset configuration word field, shown in Table 4-11, specifies both the device boot
ROM address window and the initial e300 core boot address.
12–13 RLEXT Boot ROM location extension.
This bit combined with bit ROMLOC determines where the device boots from. See Section 4.3.2.2.3,
“Boot ROM Location,” for more information.
00 Legacy mode—allows for booting from on-chip peripherals. For more information, see Ta ble 4-13.
01 NAND Flash mode—allows for booting from NAND flash devices. For more information, see
Ta ble 4 -1 3.
10 Reserved
11 Reserved
14–15 — Reserved, should be cleared.
16–18 TSEC1M TSEC1 mode
See Section 4.3.2.2.4, “eTSEC1 Mode,” for more information.
19–21 TSEC2M TSEC2 mode.
See Section 4.3.2.2.5, “eTSEC2 Mode,” for more information.
22–27 — Reserved, should be cleared.
28 TLE True little-endian. See Section 4.3.2.2.6, “e300 Core True Little-Endian,” for more information.
29–31 — Reserved, should be cleared.
Table 4-11. Boot Memory Space
RCWHR Bit Field Name
Value
(Binary)
Meaning
5 BMS 0 Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF.
e300 core register MSR[IP] initial value is 0b0.
The core, if enabled to boot, begins fetching boot code from address 0x0000_0100
and exceptions are vectored to the physical address of 0x000n_nnnn.
1 Boot memory space is 8 Mbytes at 0xFF80_0000 to 0xFFFF_FFFF.
e300 core register MSR[IP] initial value is 0b1.
The core, if enabled to boot, begins fetching boot code from address 0xFFF0_0100
and exceptions are vectored to the physical address of 0xFFFn_nnnn.
Table 4-10. Reset Configuration Word High Bit Settings (continued)
Bits Name Description