Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-11
A.16 Enhanced Local Bus Controller (eLBC)
Table A-16. Enhanced Local Bus Controller Registers
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Offset Register Access Reset Section/Page
0x000 BR0—Base register 0 R/W 0x0000_nnnn 10.3.1.1/10-9
0x008 BR1—Base register 1 R/W 0x0000_0000 10.3.1.1/10-9
0x010 BR2—Base register 2 R/W 0x0000_0000 10.3.1.1/10-9
0x018 BR3—Base register 3 R/W 0x0000_0000 10.3.1.1/10-9
0x020–0x038 Reserved — — —
0x004 OR0—Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-10
0x00C OR1—Options register 1 R/W 0x0000_0000 10.3.1.2/10-10
0x014 OR2—Options register 2 R/W 0x0000_0000 10.3.1.2/10-10
0x01C OR3—Options register 3 R/W 0x0000_0000 10.3.1.2/10-10
0x024–
0x064
Reserved — — —
0x068 MAR—UPM address register R/W 0x0000_0000 10.3.1.3/10-18
0x06C Reserved — — —
0x070 MAMR—UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19
0x074 MBMR—UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19
0x078 MCMR—UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19
0x07C–
0x080
Reserved — — —
0x084 MRTPR—Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21
0x088 MDR—UPM/FCM data register R/W 0x0000_0000 10.3.1.6/10-21
0x08C Reserved — — —
0x090 LSOR—Special operation initiation register R/W 0x0000_0000 10.3.1.7/10-22
0x094–
0x09C
Reserved — — —
0x0A0 LURT—UPM refresh timer R/W 0x0000_0000 10.3.1.4/10-19
0x0A4–
0x0AC
Reserved — — —
0x0B0 LTESR—Transfer error status register w1c 0x0000_0000 10.3.1.9/10-24
0x0B4 LTEDR—Transfer error disable register R/W 0x0000_0000 10.3.1.10/10-26
0x0B8 LTEIR—Transfer error interrupt register R/W 0x0000_0000 10.3.1.11/10-27
0x0BC LTEATR—Transfer error attributes register R/W 0x0000_0000 10.3.1.12/10-28
0x0C0 LTEAR—Transfer error address register R/W 0x0000_0000 10.3.1.13/10-29