Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-9
A.14 I
2
C Controller
0xE00 DATA_ERR_INJECT_HI—Memory data path error injection mask
high
R/W 0x0000_0000 9.4.1.18/9-30
0xE04 DATA_ERR_INJECT_LO—Memory data path error injection mask
low
R/W 0x0000_0000 9.4.1.19/9-31
0xE08 ERR_INJECT—Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-31
0xE20 CAPTURE_DATA_HI—Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32
0xE24 CAPTURE_DATA_LO—Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-32
0xE28 CAPTURE_ECC—Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33
0xE40 ERR_DETECT—Memory error detect w1c 0x0000_0000 9.4.1.24/9-33
0xE44 ERR_DISABLE—Memory error disable R/W 0x0000_0000 9.4.1.25/9-34
0xE48 ERR_INT_EN—Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35
0xE4C CAPTURE_ATTRIBUTES—Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36
0xE50 CAPTURE_ADDRESS—Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37
0xE54 Reserved — — —
0xE58 ERR_SBE—Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37
1
Implementation-dependent reset values are listed in specified section/page.
Table A-14. I
2
C Controller Registers
I
2
C Controller 1 —Block Base Address 0x0_3000
I
2
C Controller 2 —Block Base Address 0x0_3100
Offset Register Access Reset Section/Page
0x000 I2CADR—I2C address register R/W 0x0000 17.3.1.1/17-5
0x004 I2CFDR—I2C frequency divider register R/W 0x0000 17.3.1.2/17-5
0x008 I2CCR—I2C control register R/W 0x0000 17.3.1.3/17-6
0x00C I2CSR—I2C status register R/W 0x0081 17.3.1.4/17-8
0x010 I2CDR—I2C data register R/W 0x0000 17.3.1.5/17-9
0x014 I2CDFSRR—I2C digital filter sampling rate register R/W 0x0010 17.3.1.6/17-10
0x01C–0x1FF Reserved — — —
Table A-13. DDR Memory Controller Registers (continued)
DDR Memory Controller—Block Base Address 0x0_2000
Offset Register Access Reset Section/Page