Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-8 Freescale Semiconductor
A.12 General Purpose I/O (GPIO)
A.13 DDR Memory Controller
Table A-12. General Purpose I/O (GPIO) Registers
General Purpose I/O (GPIO)—Block Base Address 0x0_0C00
Offset Register Access Reset Section/Page
0x000 GPIO direction register (GPDIR) R/W 0x0000_0000 21.3.1/21-3
0x004 GPIO open drain register (GPODR) R/W 0x0000_0000 21.3.2/21-3
0x008 GPIO data register (GPDAT) R/W 0x0000_0000 21.3.3/21-4
0x00C GPIO interrupt event register (GPIER) w1c Undefined 21.3.4/21-4
0x010 GPIO interrupt mask register (GPIMR) R/W 0x0000_0000 21.3.5/21-4
0x014 GPIO external interrupt control register (GPICR) R/W 0x0000_0000 21.3.6/21-5
Table A-13. DDR Memory Controller Registers
DDR Memory Controller—Block Base Address 0x0_2000
Offset Register Access Reset Section/Page
0x000 CS0_BNDS—Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10
0x008 CS1_BNDS—Chip select 1 memory bounds R/W 0x0000_0000 9.4.1.1/9-10
0x080 CS0_CONFIG—Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11
0x084 CS1_CONFIG—Chip select 1 configuration R/W 0x0000_0000 9.4.1.2/9-11
0x100 TIMING_CFG_3—DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13
0x104 TIMING_CFG_0—DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14
0x108 TIMING_CFG_1—DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16
0x10C TIMING_CFG_2—DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18
0x110 DDR_SDRAM_CFG—DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-19
0x114 DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22
0x118 DDR_SDRAM_MODE—DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-23
0x11C DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24
0x120 DDR_SDRAM_MD_CNTL—DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25
0x124 DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27
0x128 DDR_DATA_INIT—DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28
0x130 DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28
0x140–0x144 Reserved — — —
0x148 DDR_INIT_ADDR—DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29
0x150–0xBF4 Reserved — — —
0xBF8 DDR_IP_REV1—DDR IP block revision 1 R 0xnnnn_nnnn
1
9.4.1.16/9-29
0xBFC DDR_IP_REV2—DDR IP block revision 2 R 0x00nn_00nn
1
9.4.1.17/9-30