Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-7
A.10 Clock Configuration
A.11 Power Management Controller (PMC)
0x010 Reset status register (RSR) R/W 0x0000_0000 4.5.1.3/4-26
0x014 Reset mode register (RMR) R/W 0x0000_0000 4.5.1.4/4-27
0x018 Reset protection register (RPR) R/W 0x0000_0000 4.5.1.5/4-28
0x01C Reset control register (RCR) R/W 0x0000_0000 4.5.1.6/4-28
0x020 Reset control enable register (RCER) R/W 0x0000_0000 4.5.1.7/4-29
0x024 Reserved — — —
0x028–
0x0FC
Reserved, should be cleared — — —
Table A-10. Clock Configuration Registers
Clock Configuration—Block Base Address 0x0_0A00
Offset Register Access Reset Section/Page
0x000 System PLL mode register (SPMR) R 0xnnnn_nnnn 4.5.2.1/4-30
0x004 Output clock control register (OCCR) R/W 0x0000_E080 4.5.2.2/4-31
0x008 System clock control register (SCCR) R/W 0x5550_0010 4.5.2.3/4-32
0x00C–0x0FC Reserved, should be cleared — — —
Table A-11. Power Management Controller (PMC) Registers
Power Management Controller—Block Base Address 0x0_0B00
Offset Register Access Reset Section/Page
0x000 Power management controller configuration register (PMCCR) R/W 0x0000_0000 5.7.2.1/5-70
0x004–0x0FC Reserved — — —
Table A-9. Reset Configuration Registers (continued)
Reset Configuration—Block Base Address 0x0_0900
Offset Register Access Reset Section/Page