Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-6 Freescale Semiconductor
A.8 System Arbiter
A.9 Reset Configuration
0x058 System external interrupt force register (SEFCR) R/W 0x0000_0000 8.5.20/8-29
0x05C System error force register (SERFR) R/W 0x0000_0000 8.5.21/8-29
0x060 System critical interrupt vector register (SCVCR) R 0x0000_0000 8.5.22/8-30
0x064 System management interrupt vector register (SMVCR) R 0x0000_0000 8.5.23/8-30
0x068–0x0BF Reserved — — —
Table A-8. System Arbiter Registers
System Arbiter—Block Base Address 0x0_0800
Offset Register Access Reset Section/Page
0x00 Arbiter configuration register (ACR) R/W 0x0000_0000/
0x0010_0000
1
1
Reset value is determined from the core PLL configuration of the reset configuration word. See Chapter 4, “Reset, Clocking,
and Initialization,” for details.
6.2.1/6-3
0x04 Arbiter timers register (ATR) R/W FFFF_FFFF 6.2.2/6-4
0x08 Arbiter Event Enable Register (AEER) R/W 0x0000_003F 6.2.3/6-5
0x0C Arbiter event register (AER) w1c 0x0000_0000 6.2.4/6-6
0x10 Arbiter interrupt definition register (AIDR) R/W 0x0000_0000 6.2.5/6-7
0x14 Arbiter mask register (AMR) R/W 0x0000_0000 6.2.6/6-8
0x18 Arbiter event attributes register (AEATR) R 0x0000_0000
2
2
The registers AEATR and AEADR are affected only by the assertion of PORESET.
6.2.7/6-9
0x1C Arbiter event address register (AEADR) R 0x0000_0000
2
6.2.8/6-10
0x20 Arbiter event response register (AERR) R/W 0x0000_0000 6.2.9/6-11
Table A-9. Reset Configuration Registers
Reset Configuration—Block Base Address 0x0_0900
Offset Register Access Reset Section/Page
0x000 Reset configuration word low register (RCWLR) R 0x0000_0000 4.5.1.1/4-25
0x004 Reset configuration word high register (RCWHR) R 0x0000_0000 4.5.1.2/4-25
0x008–
0x00C
Reserved, should be cleared — — —
Table A-7. IPIC Registers (continued)
Integrated Programmable Interrupt Controller—Block Base Address 0x0_0700
Offset Register Access Reset Value Section/Page