Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-4 Freescale Semiconductor
A.6 General Purpose (Global) Timers (GTMs)
0x010 Periodic interval timer event register (PTEVR) w1c 0x0000_0000 5.5.5.5/5-51
0x014–0x01F Reserved — — —
Table A-6. General Purpose (Global) Timers (GTMs) Registers
Offset Register Access
Reset
Value
Section/Page
General Purpose (Global) Timer Module 1—Block Base Address 0x0_0500
0x000 Timer 1 and 2 global timers configuration register (GTCFR1) R/W 0x0000 5.6.5.1/5-58
0x001–0x003 Reserved — — —
0x004 Timer 3 and 4 global timers configuration register (GTCFR2) R/W 0x0000 5.6.5.1/5-58
0x005–0x00F Reserved — — —
0x010 Timer 1 global timers mode register (GTMDR1) R/W 0x0000 5.6.5.2/5-62
0x012 Timer 2 global timers mode register (GTMDR2)
0x014 Timer 1 global timers reference register (GTRFR1) R/W 0xFFFF 5.6.5.3/5-63
0x016 Timer 2 global timers reference register (GTRFR2)
0x018 Timer 1 global timers capture register (GTCPR1) R/W 0x0000 5.6.5.4/5-63
0x01A Timer 2 global timers capture register (GTCPR2)
0x01C Timer 1 global timers counter register (GTCNR1) R/W 0x0000 5.6.5.5/5-64
0x01E Timer 2 global timers counter register (GTCNR2)
0x020 Timer 3 global timers mode register (GTMDR3) R/W 0x0000 5.6.5.2/5-62
0x022 Timer 4 global timers mode register (GTMDR4)
0x024 Timer 3 global timers reference register (GTRFR3) R/W 0xFFFF 5.6.5.3/5-63
0x026 Timer 4 global timers reference register (GTRFR4)
0x028 Timer 3 global timers capture register (GTCPR3) R 0x0000 5.6.5.4/5-63
0x02A Timer 4 global timers capture register (GTCPR4)
0x02C Timer 3 global timers counter register (GTCNR3) R/W 0x0000 5.6.5.5/5-64
0x02E Timer 4 global timers counter register (GTCNR4)
0x030 Timer 1 global timers event register (GTEVR1) w1c 0x0000 5.6.5.6/5-64
0x032 Timer 2 global timers event register (GTEVR2)
0x034 Timer 3 global timers event register (GTEVR3)
0x036 Timer 4 global timers event register (GTEVR4)
Table A-5. Periodic Interval Timer (PIT) Registers (continued)
Periodic Interval Timer (PIT)—Block Base Address 0x0_0400
Offset Register Access Reset Section/Page