Information
Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-12 Freescale Semiconductor
4.3.2.2 Reset Configuration Word High Register (RCWHR)
RCWHR is shown in Figure 4-4. This read-only register gets its values according to the reset configuration
word high loaded during the reset flow.
Table 4-10 defines the reset configuration word high bit fields.
Offset 0x0_0904 Access: Read/Write
0 3 4 5 6 7 8 9 11 12 13 14 15
Field —
CORE
DIS
BMS BOOTSEQ SWEN ROMLOC RLEXT —
16 18 19 21 22 27 28 29 30 31
Field TSEC1M TSEC2M — TLE —
Figure 4-4. Reset Configuration Word High Register (RCWHR)
Table 4-10. Reset Configuration Word High Bit Settings
Bits Name Description
0–3 — Reserved, should be cleared
4 COREDIS Core disable mode. Specifies the e300 core mode out of reset. If COREDIS is set, the core cannot fetch
boot code until it is configured by an external master. The external master frees the core to boot by
clearing the COREDIS bit in the arbiter configuration register as described in Section 6.2.1, “Arbiter
Configuration Register (ACR).”
This bit must be set when the boot sequencer is enabled to initiate the device (BOOTSEQ is not 0b00).
Otherwise, unpredictable behavior occurs.
0 The core can boot without waiting for configuration by an external master.
1 Core boot hold-off mode. The core is prevented from booting until it is configured by an external
master.
5 BMS Boot memory space.
See Section 4.3.2.2.1, “Boot Memory Space (BMS),” for more information.
6–7 BOOTSEQ Boot sequencer configuration.
See Section 4.3.2.2.2, “Boot Sequencer Configuration,” for more information.
8 SWEN Software watchdog enable. Selects whether the software watchdog is enabled to start counting down
immediately when coming out of reset. The user can override this value by writing to the system
watchdog control register (SWCRR[SWEN]) during system initialization.
0 Disabled
1 Enabled
9–11 ROMLOC Boot ROM interface location.
This bit combined with bit RLEXT determines where the device boots from. See Section 4.3.2.2.3, “Boot
ROM Location,” for more information.