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1131

Complete List of Configuration, Control, and Status Registers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

A-2 Freescale Semiconductor

A.2 System Configuration Registers

0x0A8 DDR2 local access window 1 base address register

(DDRLAWBAR1)

R/W 0x0000_0000 5.1.4.7/5-11

0x0AC DDR2 local access window 1 attribute register

(DDRLAWAR1)

R/W 0x0000_0000 5.1.4.8/5-12

0x0B0–0x0FC Reserved — — —

Depends on reset configuration word high values. See Section 5.1.4.3.1, “LBLAWBAR0[BASE_ADDR] Reset Value,” for details.

Depends on reset configuration word high values. See Section 5.1.4.4.1, “LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”

for details.

Depends on reset configuration word high values. See Section 5.1.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” for

details.

Depends on reset configuration word high values. See Section 5.1.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset

Value,” for details.

Table A-2. System Configuration Registers

Local Memory

Offset (Hex)

System Configuration—Block Base Address 0x0_000

0x100 System general purpose register low (SGPRL) R/W 0x0000_0000 5.2.2.1/5-16

0x104 System general purpose register high (SGPRH) R/W 0x0000_0000 5.2.2.2/5-16

0x108 System part and revision ID register (SPRIDR) R 0x8101_01nn 5.2.2.3/5-17

0x10C Reserved — — —

0x110 System priority configuration register (SPCR) R/W 0x0000_0000 5.2.2.4/5-17

0x114 System I/O configuration register low (SICRL) R/W 0x0000_0000

Bit #25 depends on the RCW.

5.2.2.5/5-19

0x118 System I/O configuration register high (SICRH) R/W

0x0014_5000

Bit #30 depend on RCW.

5.2.2.6/5-22

0x11C–0x124 Reserved — — —

0x128 DDR control driver register (DDRCDR) R/W 0x0000_0000 5.2.2.9/5-26

0x12C DDR debug status register (DDRDSR) R 0x3300_0000 5.2.2.10/5-28

0x140 PCI Express control register 1 (PECR1) R/W 0x0000_0000 5.2.2.11/5-28

0x144 eSDHC Control Regiser (SDHCCR) R/W 0x0000_0000 5.2.2.12/5-30

0x148 RTC Control Register (RTCCR) R/W 0x0000_0000 5.2.2.13/5-32

0x160–0x1FC Reserved — — —

Table A-1. Local Access Register Memory Map (continued)

Local Access—Block Base Address 0x0_000

Local Memory

Offset (Hex)