Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-1
Appendix A
Complete List of Configuration, Control, and Status
Registers
A.1 Local Access Windows
Table A-1. Local Access Register Memory Map
Local Access—Block Base Address 0x0_000
Local Memory
Offset (Hex)
Register Access Reset Section/Page
0x000 Internal memory map base address register (IMMRBAR) R/W 0xFF40_0000 5.1.4.1/5-5
0x004 Reserved — — —
0x008 Alternate configuration base address register (ALTCBAR) R/W 0x0000_0000 5.1.4.2/5-7
0x00C–0x01C Reserved — — —
0x020 eLBC local access window 0 base address register
(LBLAWBAR0)
R/W 0x0000_0000
1
5.1.4.3/5-7
0x024 eLBC local access window 0 attribute register (LBLAWAR0) R/W 0x0000_0000
2
5.1.4.4/5-8
0x028 eLBC local access window 1 base address register
(LBLAWBAR1)
R/W 0x0000_0000 5.1.4.3/5-7
0x02C eLBC local access window 1 attribute register (LBLAWAR1) R/W 0x0000_0000 5.1.4.4/5-8
0x030 eLBC local access window 2 base address register
(LBLAWBAR2)
R/W 0x0000_0000 5.1.4.3/5-7
0x034 eLBC local access window 2 attribute register (LBLAWAR2) R/W 0x0000_0000 5.1.4.4/5-8
0x038 eLBC local access window 3 base address register
(LBLAWBAR3)
R/W 0x0000_0000 5.1.4.3/5-7
0x03C eLBC local access window 3 attribute register (LBLAWAR3) R/W 0x0000_0000 5.1.4.4/5-8
0x040–0x063C Reserved — — —
0x064 Reserved — — —
0x068-0x07C Reserved — — —
0x080 PCI Express local access window base address register
(PCIEXP1LAWBAR)
R/W 0x0000_0000 5.1.4.5/5-9
0x084 PCI Express local access window attribute register
(PCIEXP1LAWAR)
R/W 0x0000_0000 5.1.4.6/5-10
0x088–0x09C Reserved — — —
0x0A0 DDR2 local access window 0 base address register
(DDRLAWBAR0)
R/W 0x0000_0000
3
5.1.4.7/5-11
0x0A4 DDR2 local access window 0 attribute register
(DDRLAWAR0)
R/W 0x0000_0000
4
5.1.4.8/5-12