Information

General Purpose I/O (GPIO)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 21-5
of the GPIMR state. When one or more non-masked interrupt events occur, the GPIO module issues an
interrupt to the on chip interrupt controller.
Table 21-7 defines the bit fields of GPIMR.
21.3.6 GPIO Interrupt Control Register (GPICR)
The GPIO interrupt control register (GPICR), shown in Figure 21-7, determines whether the
corresponding port line asserts an interrupt request on either a high-to-low change or any change on the
state of the signal.
Table 21-8 defines the bit fields of GPICR.
Offset 0xC10 Access: Read/write
0 23 24 31
R
Dn —
W
Reset All zeros
Figure 21-6. GPIO Interrupt Mask Register (GPIMR)
Table 21-7. GPIMR Bit Settings
Bits Name Description
0–23 Dn Interrupt mask. Indicates whether an interrupt event is masked or not masked.
0 The input interrupt signal is masked (disabled).
1 The input interrupt signal is not masked (enabled).
24–31 — Reserved
Offset 0xC14 Access: Read/write
0 23 24 31
R
Dn —
W
Reset All zeros
Figure 21-7. GPIO Interrupt Control Register (GPICR)
Table 21-8. GPICR Bit Settings
Bits Name Description
0–23 Dn Edge detection mode. The corresponding port line asserts an interrupt request according to the following:
0 Any change on the state of the port generates an interrupt request.
1 High-to-low change on the port generates an interrupt request.
24–31 — Reserved