Information

General Purpose I/O (GPIO)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
21-4 Freescale Semiconductor
21.3.3 GPIO Data Register (GPDAT)
The GPIO data register (GPDAT), shown in Figure 21-4, carries the data in/out for the individual ports.
Table 21-5 defines the bit fields of GPDAT.
21.3.4 GPIO Interrupt Event Register (GPIER)
The GPIO interrupt event register (GPIER), shown in Figure 21-5, carries information about the events
that caused an interrupt. Each bit in GPIER, corresponds to an interrupt source. GPIER bits are cleared by
writing ones. However, writing zero has no effect.
Table 21-6 defines the bit fields of GPIER.
21.3.5 GPIO Interrupt Mask Register (GPIMR)
The GPIO interrupt mask register (GPIMR), shown in Figure 21-6, defines the interrupt masking for the
individual ports. When a masked interrupt request occurs, the corresponding GPIER bit is set, regardless
Offset 0xC08 Access: Read/write
0 23 24 31
R
Dn —
W
Reset All zeros
Figure 21-4. GPIO Data Register (GPDAT)
Table 21-5. GPnDAT Bit Settings
Bits Name Description
0–23 Dn Data. Write data is latched and presented on external signals if GPDIR has configured the port as an output.
Read operation always returns the data at the signal.
24–31 — Reserved
Offset 0xC0C Access: w1c
0 23 24 31
R
Dn —
W
Reset Undefined (the user should write 1s to clear before using)
Figure 21-5. GPIO Interrupt Event Register (GPIER)
Table 21-6. GPIER Bit Settings
Bits Name Description
0–23 Dn Interrupt events. Indicates whether an interrupt event occurred on the corresponding GPIO signal.
0 No interrupt event occurred on the corresponding GPIO signal.
1 Interrupt event occurred on the corresponding GPIO signal.
24–31 — Reserved