Information

General Purpose I/O (GPIO)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
21-2 Freescale Semiconductor
• Open-drain capability on all ports
• All ports can optionally generate an interrupt upon changing their state.
21.2 External Signal Description
The following section provides information about GPIO signals.
21.2.1 Signals Overview
Table 21-1 provides detailed descriptions of the external GPIO signals.
21.3 Memory Map/Register Definition
The GPIO has programmable registers that occupy 24 bytes of memory-mapped space. Note that reading
undefined portions of the memory map returns all zeros and writing has no effect.
All GPIO registers are 32 bits wide and are located on 32-bit address boundaries. All addresses used in this
chapter are offsets from the address held in IMMRBAR as defined in Chapter 3, “Memory Map.”
Table 21-2 shows the memory map of GPIO.
Table 21-1. GPIO—Signal Descriptions
Signal I/O Description
GPIO[0:23] I/O General purpose I/O. Each signal can be set individually to act as input or output, according to application
needs.
State
Meaning
Asserted/Negated—Defined per application.
Timing Assertion/Negation—Inputs can be asserted completely asynchronously.
Outputs are asynchronous to any externally visible clock
Table 21-2. GPIO Register Address Map
Offset Register Access Reset Value Section/Page
General Purpose I/O (GPIO)—Block Base Address 0x0_0C00
0xC00 GPIO direction register (GPDIR) R/W 0x0000_0000 21.3.1/21-3
0xC04 GPIO open drain register (GPODR) R/W 0x0000_0000 21.3.2/21-3
0xC08 GPIO data register (GPDAT) R/W 0x0000_0000 21.3.3/21-4
0xC0C GPIO interrupt event register (GPIER) w1c Undefined 21.3.4/21-4
0xC10 GPIO interrupt mask register (GPIMR) R/W 0x0000_0000 21.3.5/21-4
0xC14 GPIO external interrupt control register (GPICR) R/W 0x0000_0000 21.3.6/21-5