Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-11
Table 4-8 describes the setting of SVCOD bits.
NOTE
For the frequency of operation for MPC8308, 00 is the only applicable value
of SVCOD.
4.3.2.1.2 System PLL Configuration
The system PLL ratio reset, shown in Table 4-9, establishes the clock ratio between the SYS_CLK_IN
signal and the internal csb_clk of the device. csb_clk drives internal units and feeds the e300 core PLL.
Table 4-8. System PLL VCO Division
Reset Configuration
Word Low Register
(RCWLR) Bits
Field Name
Value
(Binary)
VCO Division Factor
2–3 SVCOD 00 2
01 4
10 8
11 Reserved
Table 4-9. System PLL Ratio
RCWLR Bits Field Name
Value
(Binary)
csb_clk : SYS_CLK_IN
4–7 SPMF 0000 Reserved
0001 Reserved
0010 2 : 1
0011 3 : 1
0100 4 : 1
0101 5 : 1
0110 6 : 1
0111–1111 Reserved, should not be set