Information

JTAG/Testing Support
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
20-2 Freescale Semiconductor
• Test clock (TCK)
The TDI and TDO signals input and output all instructions and data to the JTAG scan registers. JTAG
operations are controlled by the TAP controller through the TMS and TCK signals. Boundary-scan data is
latched by the TAP controller on the rising edge of the TCK signal. The TRST signal is specified as
optional by the IEEE 1149.1 specification, and is used to reset the TAP controller asynchronously. The
assertion of the TRST signal at power-on reset ensures that the JTAG logic does not interfere with the
normal operation of the device.
20.2.1 External Signal Descriptions
The JTAG signals are summarized in Table 20-1.
Table 20-2 shows detailed descriptions of the JTAG test signals.
Table 20-1. JTAG Test Signals Summary
Name Description
Functional
Block
Function
Reset
Value
I/O
TCK Test clock Debug Clock for JTAG testing. — I
TDI Test data input Serial input for instructions and data to the JTAG test
subsystem. Internally pulled up.
—I
TDO Test data output Serial data output for the JTAG test subsystem. High
impedance except when scanning out data.
High
impedance
O
TMS Test mode select Carries commands to the TAP controller for boundary
scan operations. Internally pulled up.
—I
TRST Test reset Resets the TAP controller asynchronously. Internally
pulled up.
—I
Table 20-2. JTAG Test—Detailed Signal Descriptions
Signal I/O Description
TCK I JTAG test clock.
State
Meaning
Asserted/Negated—Should be driven by a free-running clock signal with a 30–70% duty cycle. Input
signals to the TAP are clocked in on the rising edge. Changes to the TAP output signals occur
on the falling edge. The test logic allows TCK to be stopped.
Timing See IEEE 1149.1 specification for more details.
TDI I JTAG test data input.
State
Meaning
Asserted/Negated—The value present on the rising edge of TCK is clocked into the selected JTAG
test instruction or data register. An unterminated input appears as a high signal level to the test
logic due to an internal pull-up resistor.
Timing See IEEE 1149.1 specification for more details.