Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 20-1
Chapter 20
JTAG/Testing Support
20.1 Overview
The device provides a JTAG (Joint Test Action Group) interface to facilitate boundary-scan testing. The
JTAG interface complies to the IEEE 1149.1 boundary-scan specification. For additional information
about JTAG operations, refer to the IEEE 1149.1 specification.
The JTAG interface consists of a set of five signals, three JTAG registers (see Section 20.3, “JTAG
Registers and Scan Chains,”) and a test access port (TAP) controller, described in the following sections.
A block diagram of the JTAG interface is shown in Figure 20-1.
Figure 20-1. JTAG Interface Block Diagram
20.2 JTAG Signals
The device provides the following five dedicated JTAG signals:
• Test data input (TDI)
• Test data output (TDO)
• Test mode select (TMS)
• Test reset (TRST)
Boundary-Scan
Register
Instruction
Register
Decoder
MUX
MUX
TAP Controller
TDI
TMS
TRST
TCK
TDO
Bypass
Register
MPC8308