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Serial Peripheral Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

19-10 Freescale Semiconductor

Figure 19-5 shows the SPI transfer format in which SPICLK starts toggling in the middle of the transfer

(SPMODE[CP] = 0).

Figure 19-5. SPI Transfer Format with SPMODE[CP] = 0

Figure 19-6 shows the SPI transfer format in which SPICLK starts toggling at the beginning of the transfer

(SPMODE[CP] = 1).

Figure 19-6. SPI Transfer Format with SPMODE[CP] = 1

19.3.1.2 SPI Event Register (SPIE)

The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an

event is recognized, the SPI sets the corresponding SPIE bit. Most SPIE bits can be cleared by writing a

19 OD Open drain mode.

0 All output pins are configured to normal mode.

1 All output pins are configured to open drain mode.

20–31 — Reserved. Should be cleared.

Table 19-4. SPMODE Field Descriptions (continued)

Bits Name Description

SPICLK

SPIMOSI

SPISEL

(From Master)

SPIMISO

(From Slave)

(CI = 0)

(CI = 1)

NOTE: Q = Undefined signal.

msb lsb

msb Qlsb