Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-10 Freescale Semiconductor
4.3.2.1 Reset Configuration Word Low Register (RCWLR)
RCWLR is shown in Figure 4-3. This read-only register obtains its values according to the reset
configuration word low loaded during the reset flow.
Table 4-7 defines the RCWLR bit fields.
4.3.2.1.1 System PLL VCO Division
The RCWLR field SVCOD (system PLL VCO division), shown in Table 4-8, establishes the internal ratio
between the system PLL VCO frequency and the PLL output clock frequency. The PLL output clock
frequency equals csb_clk frequency if RCWLR[LBCM] and RCWLR[DDRCM] are both cleared or twice
the csb_clk frequency if RCWLR[LBCM] or RCWLR[DDRCM] or both of them are set.
01234 789 15
Field LBCM DDRCM SVCOD SPMF — COREPLL
16 31
Field —
Figure 4-3. Reset Configuration Word Low Register (RCWLR)
Table 4-7. RCWLR Bit Settings
Bits Name Description
0 LBCM Local bus memory controller clock mode. Selects the local bus controller clock ratio. The local bus
memory controller operates with a frequency equal to the frequency of csb_clk. This bit should be cleared.
LBC controller clock: csb_clk
0 1:1
Note: This bit should always be set to 0.
1 DDRCM DDR SDRAM memory controller clock mode. Selects the DDR SDRAM memory controller clock ratio.
The DDR SDRAM memory controller operates at twice the frequency of the csb_clk.
1 csb_clk ratio is 2:1
Note: This bit should always be set to 1.
2–3 SVCOD System PLL VCO division. See Section 4.3.2.1.1, “System PLL VCO Division.”
4–7 SPMF System PLL multiplication factor.
See Section 4.3.2.1.1, “System PLL VCO Division,” for more information.
8 — Reserved, should be cleared
9–15 COREPLL Core PLL configuration. COREPLL sets the ratio between the e300 core clock and the internal csb_clk of
the device. For information on the encodings for COREPLL, see MPC8308 PowerQUICC II Pro Processor
Hardware Specification.
16–31 — Reserved, should be cleared.