Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 19-9
2 CI Clock invert. Inverts SPI clock polarity. See Figure 19-5 and Figure 19-6 for more information
0 The inactive state of SPICLK is low.
1 The inactive state of SPICLK is high.
3 CP Clock phase. Selects the transfer format. See Figure 19-5 and Figure 19-6 for more information.
0 SPICLK starts toggling at the middle of the data transfer.
1 SPICLK starts toggling at the beginning of the data transfer.
4 DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator (SPI BRG) when configured as an SPI
master. In slave mode, SPICLK is the clock source.
0 The SPI block input clock is the input to the SPI BRG.
1 The SPI block input clock/16 is the input to the SPI BRG.
In slave mode, this bit must be cleared.
5 REV Reverse data mode for 8-/16-/32-bit character length only (see Section 19.3.1.6.1, “Reverse Mode
SPMODE[REV] Examples.”)
0 LSB sent/received first (for data LEN < 32 the data is located at the lower half-word LSB)
1 MSB sent/received first
6 M/S Master/slave. Selects master or slave mode.
0 The SPI is a slave.
1 The SPI is a master.
7 EN Enable SPI. Any other bits in SPMODE must not change when EN is set.
0 The SPI is disabled. The SPI is in a idle state and consumes minimal power. The SPI BRG is not
functioning and the input clock is disabled.
1 The SPI is enabled.
Note: The SPI controller requires a minimal gap of at least 10 input clocks between disabling the SPI and
re-enabling. This minimal gap is sufficient provided that SPMODE[PM] and SPMODE[DIV16] are
cleared during the time in which SPMODE[EN] is cleared.
8–11 LEN Character length in bits per character. LEN can be either 32-bits, or 4- to 16-bits that are shown as follows:
0000 32-bit characters
0001–0010 Reserved, causes erratic behavior.
0011 4-bit characters
…
1111 16-bit characters
The TX and RX registers (SPITD, SPIRD) hold 32 bits at a time. A character length of 32 bits fills the TX and
RX registers; therefore, all of the bits in these registers are valid. However, if the character length selected by
LEN is equal or less than 16 bits, then the valid bits will reside in the lower half-word of the transmit and receive
registers. For example, if the character length is set to 16 bits than the valid bits will be 16–31, if the character
length is set to 5 bits, the valid bits are 16–20. Note that the transmit and receive registers each can hold only
one character regardless of the character length.
12–15 PM Prescale modulus select. Specifies the divide ratio of the prescale divider in the SPI clock generator. The SPI
baud rate generator clock source (either input clock or input clock divided by 16, depending on DIV16 bit) is
divided by 4  ([PM] + 1), a range from 4 to 64. The clock has a 50% duty cycle. For example, if the prescale
modulus is set to PM = 0011 and DIV16 is set, the system/SPICLK clock ratio will be
16  (4  (0011 + 1)) = 256.
In slave mode, this field must be cleared.
16–18 — Reserved. Should be cleared.
Table 19-4. SPMODE Field Descriptions (continued)
Bits Name Description