Information

Serial Peripheral Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

19-8 Freescale Semiconductor

of IMMRBAR together with the SPI block base address and offset listed in Table 19-3. Undefined 4-byte

address spaces within offset 0x000–0xFFF are reserved.

19.3.1 Register Descriptions

This section describes the registers listed in Table 19-3.

19.3.1.1 SPI Mode Register (SPMODE)

SPMODE, shown in Figure 19-4, controls both the SPI operation mode and clock source.

Table 19-4 describes the SPMODE fields.

Table 19-3. SPI Register Summary

Offset Register Access Reset Value Section/Page

Serial Peripheral Interface (SPI)—Block Base Address 0x0_7000

0x000–0x01F Reserved — — —

0x020 SPI mode register (SPMODE) R/W 0x0000_0000 19.3.1.1/1919-8

0x024 SPI event register (SPIE) Mixed 0x0000_0000 19.3.1.2/1919-11

0x028 SPI mask register (SPIM) R/W 0x0000_0000 19.3.1.3/1919-12

0x02C SPI command register (SPCOM) W 0x0000_0000 19.3.1.4/1919-13

0x030 SPI transmit register (SPITD) W 0x0000_0000 19.3.1.5/1919-13

0x034 SPI receive register (SPIRD) R 0xFFFF_FFFF 19.3.1.6/1919-14

0x038–0xFFF Reserved — — —

Offset 0x020 Access: Read/write

0 1 2 3 4 5 6 7 8 11 12 15 16 18 19 20 31

— LOOP CI CP DIV16 REV M/S EN LEN PM — OD —

Reset All zeros

Figure 19-4. SPMODE-SPI Mode Register Definition

Table 19-4. SPMODE Field Descriptions

Bits Name Description

0 — Reserved. Should be cleared.

1 LOOP Loop mode. Enables local loopback operation.

0 Normal operation.

1 Loopback mode. Used to test the SPI controller internal functionality, the transmitter output is internally

connected to the receiver input. The receiver and transmitter operate normally, except that received data

is ignored.

The SPI acts normally in loop back mode; therefore, negating SPISEL in slave mode stops transmission,

negating it in master mode and causing and MME error.