Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 19-5
the output drivers of the SPI signals. The core must clear SPMODE[EN], correct the problems, and clear
SPIE[MME] before the SPI can be used again.
Figure 19-3. Multiple-Master Configuration
The maximum sustained data rate that the SPI supports is input clock/50. However, the SPI can transfer a
single character at much higher rates—input clock/4 in master mode and input clock/2 in slave mode. Gaps
should be inserted between multiple characters to keep from exceeding the maximum sustained data rate.
SPI #0
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT1
SELOUT2
SELOUT3
Notes:
All signals are open-drain.
For a multiple-master configuration with more than two masters, SPISEL
and SPIE[MME]
do not detect all possible conflicts.
It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example).
SELOUT
x signals are implemented in software with general-purpose I/O signals.
1.
2.
3.
4.
SPISEL0
SPISEL1
SPISEL2
SPISEL3
SPI #1
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT2
SELOUT3
SPI #2
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT1
SELOUT3
SPI #3
SPIMOSI
SPIMISO
SPICLK
SPISEL
SELOUT0
SELOUT1
SELOUT2