Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
19-4 Freescale Semiconductor
The SPI sets SPIE[NF] to issue a maskable interrupt to the interrupt controller whenever its transmit buffer
is not full. It also sets the NF bit after sending the last word. In response, the core should read the exception
flags that relate to the last word. The SPI sets SPIE[NE] to issue a maskable interrupt to the interrupt
controller whenever the receiver buffer has been filled with data.
19.1.3.2 SPI as a Slave Device
In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slave’s
SPISEL must be asserted before Rx clocks are recognized. Once SPISEL is asserted, SPICLK becomes an
input from the master to the slave. SPICLK can be any frequency from DC to input clock/2.
To prepare for data transfers, the core writes data to be sent into the SPITD register. Once SPISEL is
asserted, the slave shifts data out from SPIMISO and in through SPIMOSI. The SPI sets the NF bit of the
SPIE register and a maskable interrupt is issued when a full buffer finishes receiving and sending or after
an error. The SPI continues reception until SPISEL is negated.
Transmission continues until no more data is available or SPISEL is negated. Transmission continues once
SPISEL is reasserted and SPICLK begins toggling. After the characters in the buffer are sent, the SPI sends
one as long as SPISEL remains asserted.
19.1.3.3 SPI in Multiple-Master Operation
The SPI can operate in a multiple-master environment in which all SPI devices are connected to the same
bus. In this configuration, the SPIMOSI, SPIMISO, and SPICLK signals of all SPIs are shared; but the
SPISEL inputs are connected separately, as shown in Figure 19-3. Only one SPI device can act as master
at a time—all others must be slaves. When a SPI is configured as a master, if its SPISEL input is asserted,
a multiple-master error occurs because more than one SPI device is a bus master. The SPI sets SPIE[MME]
in the SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and