Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 19-3
19.1.3 Modes of Operation
The SPI can be programmed to work in a single- or multiple-master environment. This section describes
SPI master and slave operations in a single-master configuration. It also discusses the multiple master
environment.
The following sections summarize the main modes of operation that the SPI supports.
19.1.3.1 SPI as a Master Device
In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
A single master device with multiple slaves can use general-purpose parallel I/O signals to selectively
enable slaves, as shown in Figure 19-2. To eliminate the multi-master error in a single-master
environment, the master’s SPISEL input should be forced inactive by an external pull up.
Figure 19-2. Single-Master/Multi-Slave Configuration
To start exchanging data, the processor core writes the data to be sent into the SPITD register. The SPI then
generates programmable clock pulses on SPICLK for each character. It shifts Tx data out on the SPI
master-out slave-in (SPIMOSI) and Rx data in on the SPI master-in slave-out (SPIMISO) simultaneously.
During transmission, the core is responsible for supplying the data whenever the SPI requests it to ensure
smooth operation. After the last data (LST command and data afterwards), the first character written to
SPITD acts as a start command for the SPI.
The SPI continues transmitting and receiving characters until SPCOM[LST] is set or an error occurs.
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 0
SPIMISO
SPICLK
SPISEL
Slave 1
Slave 2
Master SPI
SPIMOSI
SPIMISO
SPICLK
SPISEL
SPIMOSI
SPICLK
SPIMISO
SPIMOSI
GPIOx
GPIOy
GPIOz