Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
19-2 Freescale Semiconductor
19.1.1 Features
The major features of the SPI are listed as follows:
• Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL)
• Full-duplex operation
• Works with 32-bit data characters or with a range from 4-bit to 16-bit data characters
• Supports back-to-back character transmission and reception
• Supports reverse data mode for 8/16/32 character length
• Supports master SPI mode
• Supports multiple-master environment
• Maximum clock rate is (input clock rate/4) in master mode; (input clock rate/2) in slave mode
• Independent programmable baud rate generator
• Programmable clock phase and polarity
• Local loopback capability for testing
• Open-drain outputs support multiple-master configuration
19.1.2 SPI Transmission and Reception Process
Because the SPI is a character-oriented communication unit, the core is responsible for packing and
unpacking the receive and transmit frames. A frame consists of all of the characters transmitted or received
during a completed SPI transmission session, from the first character written to the SPITD register to the
last character transmitted following the setting of SPCOM[LST]. See Section 19.3.1.4, “SPI Command
Register (SPCOM),” for more information.
The core receives data by reading the SPI receive data hold register (SPIRD). The SPI then clears the not
empty SPIE[NE] to free up the SPIRD register for the next receive operation. The core transmits data by
writing it into the SPI transmit data hold register (SPITD). The SPI then clears the not full (NF) bit in the
SPI event register (SPIE) to indicate that the SPITD register contains a character for transmission. When
the next character to be transmitted is going to be the final one in the current frame, the core sets
SPCOM[LST], and then writes the final character to SPITD.
The SPI core handshake protocol can be implemented by either using polling or interrupts.When using a
polling, the core reads the SPIE in a predefined frequency and acts according to the value of the SPIE
bits.The polling frequency depends on the SPI serial channel frequency.When using the interrupt
mechanism, setting either the not full (NF) or not empty (NE) bits of SPIE causes an interrupt to the
processor core.The core then reads SPIE and acts accordingly. The three basic modes of operation for
transmitting and receiving are master, slave and multiple-master.
NOTE
When both NE and NF bits are set, the processor core should read the
received data before transmitting new data.
The SPMODE[LEN] determines the character length sent by the hardware. The core is responsible for any
bit manipulation to pack/unpack data into the appropriate character length. See the SPMODE[LEN]
description in Table 19-4 for more information.