Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-9
4.3.1.2 Selecting Reset Configuration Input Signals
The example described in Table 4-6 shows how the user should pull down or pull up the reset configuration
input signal (CFG_RESET_SOURCE). The reset sequence duration is measured from the negation of
PORESET
to the negation of HRESET. Note that the duration mentioned in Table 4-6 is typical, and does
not represent cases in which the process of loading the reset configuration word had to be retried due to
errors.
4.3.2 Reset Configuration Words
The reset configuration words control the clock ratios and other basic device functions, such as, boot
location, eTSEC mode, and endian mode. The reset configuration words are loaded from NOR Flash,
NAND Flash, or the I
2
C interfaces or from hard-coded values during the power-on or hard reset flows. See
Section 4.3.1, “Reset Configuration Signals,” for information on the reset configuration word source.
Although the configuration reset words are loaded during hard reset flows, the clocks and PLL modes are
reset only when PORESET is asserted during a power-on reset flow. See Section 4.2.1.2, “Reset Actions.”
The values of fields in the reset configuration words registers (RCWLR and RCWHR) reflect only their
state during the reset flow. Some of these parameters and modes can be modified by changing their values
in the memory-mapped registers of other units, which does not affect RCWLR and RCWHR.
The reset configuration settings are accessible to software through the following read-only
memory-mapped registers:
• Reset configuration word low register (RCWLR)
• Reset configuration word high register (RCWHR)
• Reset status register (RSR)
• System PLL mode register (SPMR)
See Section 4.5, “Memory Map/Register Definitions.”
Table 4-6. Selecting Reset Configuration Input Signals
I
2
C EEPROM
Configuration
Words
SYS_CLK_IN
Frequency
CFG_RESET_SOURCE[0:3]
Reset Sequence
Duration in
SYS_CLK_IN Cycles
Duration
No 33 MHz 0000
(RCW loaded from NOR Flash)
15210 456
s
Yes 33 MHz 0100 (I
2
C EEPROM) 106534 196 s