Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-21
18.5 DUART Initialization/Application Information
The following requirements must be met for DUART accesses:
• All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG
setting in the MMU needs to be 0b01x1.)
• All DUART registers must be 1 byte wide. Reads and writes to these registers must be byte-length
operations.
A system reset puts the DUART registers to a default state. Before the interface can transfer serial data,
the following initialization steps are recommended:
1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector source
registers.
2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and UDMB.
3. Set the data attributes and control bits of the external MODEM or peripheral device.
4. Set the interrupt enable register (UIER).
5. To start a write transfer, write to the UTHR.
6. Poll UIIR if the interrupts generated by the DUART are masked.