Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-20 Freescale Semiconductor
and set the FIFO receiver trigger level UFCR[RTL] to control the received data available interrupt
UIER[ERDAI].
The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the
receiver FIFO. UDSR[TXRDY] indicate when the transmitter FIFO is full. When in FIFO mode, data
written to UTHR is placed into the transmitter FIFO. The first byte written to UTHR is the first byte onto
the UART bus.
18.4.5.1 FIFO Interrupts
In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. A receive data time-out
generates a maskable interrupt condition (through UIER[ERDAI]). See Section 18.3.1.4, “Interrupt
Enable Registers (UIER1 and UIER2).”
UIIR indicates whether the FIFOs are enabled. UIIR[IID3] is set only for FIFO mode interrupts. The
character time-out interrupt occurs when no characters have been removed from or input to the receiver
FIFO during the last four character times and at least one character is in the receiver FIFO. The character
time-out interrupt (controlled by UIIR[IIDn]) is cleared when URBR is read. See Section 18.3.1.5,
“Interrupt ID Registers (UIIR1 and UIIR2).”
UIIR[FE] indicates whether FIFO mode is enabled.
18.4.5.2 DMA Mode Select
UDSR[RXRDY] reflects the status of the receiver FIFO or URBR. In mode 0 (UFCR[DMS] is cleared),
UDSR[RXRDY] is cleared when at least one character is in the receiver FIFO or URBR; it is set when
there are no more characters in the receiver FIFO or URBR. This occurs regardless of the UFCR[FEN]
setting. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[RXRDY] is cleared when the trigger
level or a time-out has been reached; it is set when there are no more characters in the receiver FIFO.
UDSR[TXRDY] reflects the status of the transmitter FIFO or UTHR. In mode 0 (UFCR[DMS] is cleared),
UDSR[TXRDY] is cleared when there are no characters in the transmitter FIFO or UTHR; it is set after
the first character is loaded into the transmitter FIFO or UTHR. This occurs regardless of the UFCR[FEN]
setting. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[TXRDY] is cleared when there are no
characters in the transmitter FIFO or UTHR; it is set when the transmitter FIFO is full.
See Section 18.3.1.12, “DMA Status Registers (UDSR1 and UDSR2),” for a complete description of the
USDR[RXRDY] and USDR[TXRDY] bits.
18.4.5.3 Interrupt Control Logic
An interrupt is active when DUART interrupt ID register bit 7 (UIIR[IID0]), is cleared. UIER is used to
mask specific interrupt types. See Section 18.3.1.4, “Interrupt Enable Registers (UIER1 and UIER2).”
When the interrupts are disabled in UIER, polling software cannot use UIIR[IID0] to determine whether
the UART is ready for service. Software must monitor the appropriate ULSR bit. UIIR[IID0] can be used
for polling if the interrupts are enabled in UIER.