Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-18 Freescale Semiconductor
18.4.1.2 Data Transfer
Each data transfer contains 5, 6, 7, or 8 bits of data. The ULCR data bit length for the transmitter and
receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur.
A transfer begins when UTHR is written. At that time, a START bit is generated followed by 5 to 8 of the
data bits previously written to the UTHR. The data bits are driven from the least- to the most-significant
bits. After the parity and STOP bits, a new data transfer can begin if new data is written to UTHR.
18.4.1.3 Parity Bit
The user has the option of using even, odd, no parity, or stick parity (see Section 18.3.1.7, “Line Control
Registers (ULCR1 and ULCR2).” Both the receiver and transmitter parity definitions must agree before
transferring data. When receiving data, a parity error can occur if an unexpected parity value is detected
(see Section 18.3.1.9, “Line Status Registers (ULSR1 and ULSR2)”).
18.4.1.4 STOP Bit
The transmitter device ends the write transfer by generating a STOP bit. The STOP bit is always high. The
user can program the length of the STOP bit(s) in the ULCR. Both the receiver and transmitter STOP bit
length must agree before attempting to transfer data. A framing error can occur if an invalid STOP bit is
detected.
18.4.2 Baud-Rate Generator Logic
Each UART contains an independent programmable baud-rate generator, that is capable of taking the
system clock input and dividing the input by any divisor from 1 to 2
16
–1.
The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula
for calculating baud rate is as follows:
Baud rate = (1/16)  (system clock frequency/divisor value) Eqn. 18-1
Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.
The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:
• UART divisor most significant byte register (UDMB)
• UART divisor least significant byte register (UDLB)
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.
The divisor latches must be loaded during initialization to ensure proper operation of the baud-rate
generator. Both UART devices on the same bus must be programmed for the same baud rate before starting
a transfer.
The baud clock can be passed to the performance monitor by enabling UAFR[BO]. This can be used to
determine baud-rate errors.