Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-17
The transmitter accepts parallel data with a write access to UTHR. In FIFO mode, the data is placed
directly into an internal transmitter shift register, or into the transmitter FIFO—see Section 18.4.5, “FIFO
Mode.” The transmitting registers convert the data to a serial bit stream by inserting the appropriate
START, STOP, and optional parity bits. Finally, the registers output a composite serial data stream on the
channel transmitter serial data output (SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into
parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the
START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or
receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR).
The receiver status may be polled or interrupt-driven.
18.4.1 Serial Interface
The UART bus is a serial, full-duplex, point-to-point bus as shown in Figure 18-15. Therefore, only two
devices are attached to the same signals and there is no need for address or arbitration bus cycles.
Figure 18-15. UART Bus Interface Transaction Protocol Example
A standard UART bus transfer is composed of either three or four parts:
• START bit
• Data transfer (least significant bit is first data bit on the bus)
• Parity bit (optional)
•STOP bits
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on
SOUT.
The following sections describe the four components of the serial interface, the baud-rate generator, local
loopback mode, different errors, and FIFO mode.
18.4.1.1 START Bit
A write to UTHR generates a START bit on the SOUT signal. Figure 18-15 shows that the START bit is
defined as a logic 0. The START bit denotes the beginning of a new data transfer which is limited to the
bit length programmed in ULCR. When the bus is idle, SOUT is high.
123456789 123456789
D6 D5
D4 D3 D2 D1 D0
PTY D6 D5 D4 D3 D2 D1 D0 PTY
rxcnt
SOUT1
START STOP Bits
Optional
Variable Data Bits Data Bits
STOP Bits
10 10
Two 7-Bit Data Transmissions with Parity and 2-Bit STOP Transactions
Even/Odd Parity