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DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-16 Freescale Semiconductor
Table 18-20 and Table 18-21 show the set and cleared conditions for UDSR[TXRDY].
Table 18-22 and Table 18-23 show the set and cleared conditions for UDSR[TRRDY].
18.4 Functional Description
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock signal.
Table 18-20. UDSR[TXRDY] Set Conditions
DMS FEN DMA Mode Meaning
0 0 0 TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
01 0
10 0
1 1 1 TXRDY is set when the transmitter FIFO is full.
Table 18-21. UDSR[TXRDY] Cleared Conditions
DMS FEN DMA Mode Meaning
0 0 0 TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
01 0
10 0
1 1 1 TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear while the transmitter FIFO is not yet full.
Table 18-22. UDSR[RXRDY] Set Conditions
DMS FEN DMA Mode Meaning
0 0 0 RXRDY is set when there are no characters in the receiver FIFO or URBR.
01 0
10 0
1 1 1 RXRDY is set when the trigger level has not been reached and there has been no time out.
Table 18-23. UDSR[RXRDY] Cleared
DMS FEN DMA Mode Meaning
0 0 0 RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
01 0
10 0
1 1 1 RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.