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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-15
Table 18-18 describes UAFR fields.
18.3.1.12 DMA Status Registers (UDSR1 and UDSR2)
The DMA status registers (UDSRs), shown in Figure 18-14, return transmitter and receiver FIFO status
and provide the ability to assist DMA data operations to and from the FIFOs.
Table 18-19 describes the fields of the UDSRs.
Table 18-18. UAFR Field Descriptions
Bits Name Description
0–5 — Reserved
6 BO Baud clock select
0 The baud clock is not gated off.
1 The baud clock is gated off.
7 CW Concurrent write enable
0 Disables writing to both UART1 and UART2.
1 Enables concurrent writes to corresponding UART registers. A write to a register in UART1 is also a write
to the corresponding register in UART2 and vice versa.
Offset: 0x0_4510, 0x0_4610 Access: User read-only
0 567
R
—
TXRDY RXRDY
W
Reset00000001
Figure 18-14. DMA Status Register (UDSR)
Table 18-19. UDSR Field Descriptions
Bits Name Description
0–5 — Reserved
6 TXRDY Transmitter ready. Reflects the status of the transmitter FIFO or the UTHR. The status depends on the DMA
mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in Table 18-21.
1 This bit is set, as shown in Table 18-20.
7 RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
the DMA mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in Table 18-23.
1 This bit is set, as shown in Table 18-22.