Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-13
18.3.1.9 Line Status Registers (ULSR1 and ULSR2)
The ULSRs, shown in Figure 18-11, monitor the status of the data transfer on the UART buses. To isolate
the status bits from the proper character received through the UART bus, software should read the ULSR
and then the URBR.
Table 18-16 describes the ULSR fields.
Offset: 0x0_4505, 0x0_4605 Access: User read-only
01234567
R RFE TEMT THRE BI FE PE OE DR
W
Reset01100000
Figure 18-11. Line Status Register (ULSR1 and ULSR2)
Table 18-16. ULSR Field Descriptions
Bits Name Description
0 RFE Receiver FIFO error.
0 Cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no remaining receiver
FIFO errors.
1 Set when one of the characters in the receiver FIFO encounters an error (framing, parity, or break
interrupt).
1 TEMT Transmitter empty
0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode, a data
character is in the transmitter FIFO or the internal transmitter shift register.
1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter
FIFO and the internal transmitter shift register are empty.
2 THRE Transmitter holding register empty
0 UTHR is not empty.
1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO mode,
the transmitter FIFO contains no data character.
3 BI Break interrupt
0 Cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received).
1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time.
A new character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected.
In FIFO mode, a zero character is encountered in the FIFO (the zero character is at the top of the FIFO).
In FIFO mode, only one zero character is stored.
4 FE Framing error
0 Cleared when ULSR is read or when a new character is loaded into the URBR from the receiver shift
register.
1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, FE is set when the
character that detected a framing error is encountered in the FIFO (that is the character at the top of the
FIFO). An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error
(due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with
the next START bit, so it assumes this logic 0 sample is a true START bit and then will receive the following
new data.
5 PE Parity error
0 Cleared when ULSR is read or when a new character is loaded into URBR.
1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is
at the top of the FIFO.