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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

18-12 Freescale Semiconductor

18.3.1.8 MODEM Control Registers (UMCR1 and UMCR2)

The UMCRs, shown in Figure 18-10, control the interface with the external peripheral device on the

UART bus.

Table 18-15 describes the UMCR fields.

Table 18-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS]

PEN SP EPS Parity Selected

000 No parity

001 No parity

010 No parity

011 No parity

1 0 0 Odd parity

101 Even parity

110 Mark parity

1 1 1 Space parity

Offset: 0x0_4504, 0x0_4604 Access: User read/write

01234567

—LOOP —

Reset All zeros

Figure 18-10. Modem Control Register (UMCR1 and UMCR2)

Table 18-15. UMCR Field Descriptions

Bits Name Description

0–2 — Reserved, should be cleared

3 LOOP Local loopback mode

0 Normal operation.

1 Functionally, the data written to UTHR can be read from URBR of the same UART

4–7 — Reserved