Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-8 Freescale Semiconductor
described in Section 4.5.1.3, “Reset Status Register (RSR),” and Section 4.5.2.1, “System PLL Mode
Register (SPMR).”
NOTE
Implement one of the following methods to control the selection between
the reset and non-reset function of these pins.
• Resistors. Use pull-up or pull-down resistors to set the desired value on
the reset configuration input signals. During the power-on and hard reset
sequences, these signals are inputs to the device.
• Active driving device. Use HRESET to control the driving device.
When HRESET is asserted, drive reset configuration values on the pins;
when HRESET is negated, stop driving the reset configuration input
signals.
4.3.1.1 Reset Configuration Word Source
The reset configuration word source options, shown in Table 4-5, select whether the device loads a reset
configuration word from NOR Flash, NAND Flash, or an I
2
C EEPROM or uses hard-coded default
options. The value of these signals also affects the duration of power-on and hard reset sequences. In any
case, the reset sequence does not exceed 1 ms.
Table 4-5. Reset Configuration Words Source
CFG_RESET_SOURCE[0:3] Meaning
0000 Reset configuration word is loaded from NOR Flash
0001 Reset configuration word is loaded from NAND Flash memory (8-bit small page).
0010 Reserved
0011 Reserved
0100 Reset configuration word is loaded from an I
2
C EEPROM. SYS_CLK_IN is in the range of
24–66.666 MHz.
0101 Reset configuration word is loaded from NAND Flash memory (8-bit large page).
0110 Reserved
0111 Reserved
1000 Hard-coded option 0. Reset configuration word is not loaded.
1001 Hard-coded option 1. Reset configuration word is not loaded.
1010 Hard-coded option 2. Reset configuration word is not loaded.
1011 Hard-coded option 3. Reset configuration word is not loaded.
1100 Hard-coded option 4. Reset configuration word is not loaded.
1101 Reserved
1110 Reserved
1111 Reserved