Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xi
Figures
Figure
Number Title
Page
Number
12.3.2 DMA Set Enable Error Interrupt (DMASEEI).......................................................... 12-9
12.3.3 DMA Clear Enable Error Interrupt (DMACEEI)...................................................... 12-9
12.3.4 DMA Clear Interrupt Request (DMACINT) ........................................................... 12-10
12.3.5 DMA Clear Error (DMACERR).............................................................................. 12-11
12.3.6 DMA Set START Bit (DMASSRT)......................................................................... 12-11
12.3.7 DMA Clear DONE Status (DMACDNE)................................................................ 12-12
12.3.8 DMA Interrupt Request Register (DMAINT) ......................................................... 12-12
12.3.9 DMA Error Register (DMAERR)............................................................................ 12-13
12.3.10 DMA General Purpose Output Register (DMAGPOR) .......................................... 12-14
12.3.11 DMA Channel n Priority (DCHPRIn), n = 0–15..................................................... 12-15
12.3.12 Transfer Control Descriptor (TCD) ......................................................................... 12-16
12.4 Functional Description................................................................................................. 12-24
12.4.1 DMA Microarchitecture .......................................................................................... 12-24
12.4.2 DMA Basic Data Flow ............................................................................................ 12-25
12.5 Initialization/Application Information......................................................................... 12-28
12.5.1 DMA Initialization................................................................................................... 12-28
12.5.2 DMA Programming Errors...................................................................................... 12-29
12.6 DMA Transfer.............................................................................................................. 12-29
12.6.1 Single Request ......................................................................................................... 12-29
12.6.2 Multiple Requests .................................................................................................... 12-30
12.7 TCD Status................................................................................................................... 12-32
12.7.1 Minor Loop Complete ............................................................................................. 12-32
12.7.2 Active Channel TCD Reads..................................................................................... 12-32
12.7.3 Preemption status..................................................................................................... 12-32
12.8 Channel Linking .......................................................................................................... 12-33
12.9 Programming during channel execution...................................................................... 12-33
12.9.1 Dynamic priority changing...................................................................................... 12-33
12.9.2 Dynamic channel linking and dynamic scatter/gather............................................. 12-34
Chapter 13
Universal Serial Bus Interface
13.1 Introduction.................................................................................................................... 13-1
13.1.1 Overview.................................................................................................................... 13-2
13.1.2 Features...................................................................................................................... 13-2
13.1.3 Modes of Operation ................................................................................................... 13-2
13.2 External Signals ............................................................................................................. 13-3
13.2.1 ULPI Interface ........................................................................................................... 13-3
13.3 Memory Map/Register Definitions................................................................................ 13-4
13.3.1 Capability Registers................................................................................................... 13-6
13.3.2 Operational Registers............................................................................................... 13-10