Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-10 Freescale Semiconductor
UFCR bits cannot be programmed unless FIFO enable bits are set. When changing from FIFO mode to
16450 mode (non-FIFO mode) and vice versa, data is automatically cleared from the FIFOs.
After all of the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared.
Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not
cleared. Both TFR and RFR are self clearing.
Figure 18-8 shows the bits in the UFCRs.
Table 18-12 describes the fields of the UFCRs.
18.3.1.7 Line Control Registers (ULCR1 and ULCR2)
The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB],
which controls the ability to access the divisor latch least and most significant bit registers and the alternate
function register.
Offset: 0x0_4502, 0x0_4602 Access: User write-only
01234567
R
W RTL — DMS TFR RFR FEN
Reset All zeros
Figure 18-8. FIFO Control Registers (UFCR1 and UFCR2)
Table 18-12. UFCR Field Descriptions
Bits Name Description
0–1 RTL Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number
of bytes in the receiver FIFO equals RTL value.
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
2–3 — Reserved
4 DMS DMA mode select. See Section 18.4.5.2, “DMA Mode Select”
0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
5 TFR Transmitter FIFO reset
0 No action
1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
6 RFR Receiver FIFO reset
0 No action
1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
7 FEN FIFO enable
0 FIFOs are disabled and cleared
1 Transmitter and receiver FIFOs are enabled.