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DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-9
Figure 18-7 shows the bits in the UIIR.
Table 18-10 describes the fields of the UIIR.
The bits contained in the UIIR registers are described in Table 18-11.
18.3.1.6 FIFO Control Registers (UFCR1 and UFCR2)
UFCR is used to enable and clear the receiver and transmitter FIFOs, set a receiver FIFO trigger level to
control the received data available interrupt, and select the type of DMA signaling.
Offset: 0x0_4502, 0x0_4602 Access: User read-only
01234567
R FE — IID3 IID2 IID1 IID0
W
Reset00000001
Figure 18-7. Interrupt ID Registers (UIIR1 and UIIR2)
Table 18-10. UIIR Field Descriptions
Bits Name Description
0–1 FE FIFOs enabled. Reflects the setting of UFCR[FEN].
2–3 — Reserved
4 IID3 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in Table 18-11. IID3 is
set along with IID2 only when a time out interrupt is pending for FIFO mode.
5–6 IID2–IID1 Interrupt ID bits identify the highest priority pending interrupt as indicated in Table 18-11.
7 IID0 IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
Table 18-11. UIIR IID Bits Summary
IID3–
IID0
Priority
Level
Interrupt Type Interrupt Description How To Reset Interrupt
0001 — — — —
0110 Highest Receiver line status Overrun error, parity error, framing error, or
break interrupt
Reading the line status register
0100 Second Received data available Receiver data available or trigger level
reached in FIFO mode.
Reading the receiver buffer
register or if the number of
bytes in the receiver FIFO
drops below the trigger level.
1100 Second Character time-out No characters were removed from or input to
the receiver FIFO during the last four
character times and at least one character is
in the receiver FIFO.
Reading the receiver buffer
register
0010 Third UTHR empty Transmitter holding register is empty. Reading UIIR or writing to
UTHR