Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-7
Figure 18-5 shows the bits in the UDLBs.
Table 18-7 describes the UDLB.
Table 18-8 shows baud rate for a variety of input clock frequencies.
To get the percent error value, the following three steps are taken:
1. The input clock frequency (ICF) is divided by the actual frequency input (AFI) to get the correct
divisor value (ICF/AFI, where AFI = baud rate  16  divisor).
2. The divisor value is subtracted from 1.
3. The result from the step two is multiplied by 100 to calculate the final percent error. The result is
calculated in absolute value (no negative numbers).
These steps can be described with the following equation:
Percent error value = (1 – AFI/ICF) 100
18.3.1.4 Interrupt Enable Registers (UIER1 and UIER2)
The UIER gives the user the ability to mask specific UART interrupts to the programmable interrupt
controller (PIC).
Offset: 0x0_4500, 0x0_4600 Access: User read/write
0 7
R
UDLB
W
Reset All zeros
Figure 18-5. Divisor Least Significant Byte Registers (UDLB1 and UDLB2)
Table 18-7. UDLB Field Descriptions
Bits Name Description
0–7 UDLB Divisor least significant byte. This is concatenated with UDMB.
Table 18-8. Baud Rate Examples
Baud Rate
(Decimal)
Divisor Input Clock
(System Clock)
Frequency
(MHz)
Percent Error
(Decimal)
Decimal Hex
9,600 866 362 133 0.013
19,200 433 1B1 133 0.013
38,400 216 D8 133 0.218
56,000 148 94 133 0.300
128,000 65 41 133 0.090
256,000 32 20 133 1.471