Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-6 Freescale Semiconductor
Figure 18-3 shows the bits in the UTHRs.
Table 18-5 describes the UTHR.
18.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
UDLB is concatenated with the divisor most significant byte register (UDMB) to create the divisor used
to divide the input clock into the DUART. The output frequency of the baud generator is 16 times the baud
rate; therefore, the desired baud rate = platform clock frequency  (16  [UDMB||UDLB]). Equivalently,
[UDMB||UDLB:0b0000] = platform clock frequency/desired baud rate. Baud rates that can be generated
by specific input clock frequencies are shown in Table 18-8.
Figure 18-4 shows the bits in the UDMBs.
Table 18-6 describes the UDMB.
Offset: 0x0_4500, 0x0_4600 Access: User write-only
0 7
R
WDATA
Reset All zeros
Figure 18-3. Transmitter Holding Registers (UTHR1 and UTHR2)
Table 18-5. UTHR Field Descriptions
Bits Name Description
0–7 DATA Data that is written to UTHR [Write only]
Offset: 0x0_4501, 0x0_4601 Access: User read/write
0 7
R
UDMB
W
Reset All zeros
Figure 18-4. Divisor Most Significant Byte Registers (UDMB1 and UDMB2)
Table 18-6. UDMB Field Descriptions
Bits Name Description
0–7 UDMB Divisor most significant byte