Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-4 Freescale Semiconductor
All DUART registers are one byte wide; reads and writes to these registers must be byte-wide operations.
Table 18-3 provides a register summary with references to the section and page that contain detailed
information about each register. Undefined byte address spaces within offset 0x4000–0x4FFF are
reserved.
Table 18-3. DUART Register Summary
Offset Register Access Reset Section/Page
UART 1—Block Base Address 0x0_4000
UART 2—Block Base Address 0x0_4100
0x0_4500 URBR—ULCR[DLAB] = 0 UART1 receiver buffer register R 0x0000 18.3.1.1/18-5
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register W 0x0000 18.3.1.2/18-5
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x0000 18.3.1.3/18-6
0x0_4501 UIER—ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x0000 18.3.1.4/18-7
UDMB—ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x0000 18.3.1.3/18-6
0x0_4502 UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register R 0x0001 18.3.1.5/18-8
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register W 0x0000 18.3.1.6/18-9
UAFR—ULCR[DLAB] = 1 UART1 alternate function register R/W 0x0000 18.3.1.11/18-14
0x0_4503 ULCR—ULCR[DLAB] = x UART1 line control register R/W 0x0000 18.3.1.7/18-10
0x0_4504 UMCR—ULCR[DLAB] = x UART1 MODEM control register R/W 0x0000 18.3.1.8/18-12
0x0_4505 ULSR—ULCR[DLAB] = x UART1 line status register R 0x0060 18.3.1.9/18-13
0x0_4506 Reserved — — —
0x0_4507 USCR—ULCR[DLAB] = x UART1 scratch register R/W 0x0000 18.3.1.10/18-14
0x0_4510 UDSR—ULCR[DLAB] = x UART1 DMA status register R 0x0001 18.3.1.12/18-15
0x0_4600 URBR—ULCR[DLAB] = 0 UART2 receiver buffer register R 0x0000 18.3.1.1/18-5
UTHR—ULCR[DLAB] = 0 UART2 transmitter holding register W 0x0000 18.3.1.2/18-5
UDLB—ULCR[DLAB] = 1 UART2 divisor least significant byte register R/W 0x0000 18.3.1.3/18-6
0x0_4601 UIER—ULCR[DLAB] = 0 UART2 interrupt enable register R/W 0x0000 18.3.1.4/18-7
UDMB—ULCR[DLAB] = 1 UART2 divisor most significant byte register R/W 0x0000 18.3.1.3/18-6
0x0_4602 UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register R 0x0001 18.3.1.5/18-8
UFCR—ULCR[DLAB] = 0 UART2 FIFO control register W 0x0000 18.3.1.6/18-9
UAFR—ULCR[DLAB] = 1 UART2 alternate function register R/W 0x0000 18.3.1.11/18-14
0x0_4603 ULCR—ULCR[DLAB] = x UART2 line control register R/W 0x0000 18.3.1.7/18-10
0x0_4604 UMCR—ULCR[DLAB] = x UART2 MODEM control register R/W 0x0000 18.3.1.8/18-12
0x0_4605 ULSR—ULCR[DLAB] = x UART2 line status register R 0x0060 18.3.1.9/18-13
0x0_4606 Reserved — — —