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DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-3
18.2 External Signal Descriptions
This section contains a signal overview and detailed signal descriptions.
18.2.1 Signal Overview
Table 18-1 summarizes the DUART signals. Note that although the actual device signal names are
prepended with the ‘UART_’ prefix as shown in the table, the functional (abbreviated) signal names are
often used throughout this chapter.
18.2.2 Detailed Signal Descriptions
The DUART signals are described in detail in Table 18-2.
18.3 Memory Map/Register Definition
There are two complete sets of DUART registers (one for UART1 and one for UART2). The two UARTs
are identical, except that the registers for UART1 are located at offsets 0x0_4500 (local) and the registers
for UART2 are located at offsets 0x0_4600 (local). Throughout this chapter, the registers are described by
a singular acronym: for example, LCR represents the line control register for either UART1 or UART2.
The registers in each UART interface are used for configuration, control, and status. The divisor latch
access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit registers and
the alternate function register. Refer to Section 18.3.1.7, “Line Control Registers (ULCR1 and ULCR2),”
for more information on ULCR[DLAB].
Table 18-1. DUART Signal Overview
Signal Name I/O Pins Reset Value State Meaning
UART_SIN[1:2] I 2 1 Serial in data UART1 and UART2
UART_SOUT[1:2] O 2 1 Serial out data UART1 and UART2
Table 18-2. DUART Signals—Detailed Signal Descriptions
Signal I/O Description
UART_SIN[1:2]/DSP
_UART_SIN
I Serial data in. Data is received on the receivers of UART1, UART2, or DSP_UART through its
respective serial data input signal, with the least significant bit received first.
State
Meaning
Asserted/Negated—Represents the data being received on the UART interface.
Timing Assertion/Negation—An internal logic sample signal, rxcnt, uses the frequency of the
baud-rate generator to sample the data on SIN.
UART_SOUT[1:2]/
DSP_UART_SOUT
O Serial data out. The serial data output signals for the UART1, UART2, or DSP_UART are set (mark
condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is
shifted out on these signals, with the least significant bit transmitted first.
State
Meaning
Asserted/Negated—Represents the data transmitted on the respective UART interface.
Timing Assertion/Negation—An internal logic sample signal, rxcnt, uses the frequency of the
baud-rate generator to update and drive the data on SOUT.