Information
DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-2 Freescale Semiconductor
18.1.1 Features
The DUART includes these features:
• Full-duplex operation
• Programming model compatible with the original PC16450 UART and the PC16550D (an
improved version of the PC16450 that also operates in FIFO mode)
• PC16450 register reset values
• FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
• Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
• Maskable transmit, receive, line status, and MODEM status interrupts
• Software-programmable baud generators that divide the system clock by 1 to (2
16
–1) and generate
a 16x clock for the transmitter and receiver engines
• Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
• Line and MODEM status registers
• Line-break detection and generation
• Internal diagnostic support, local loopback, and break functions
• Prioritized interrupt reporting
• Overrun, parity, and framing error detection
18.1.2 Modes of Operation
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock.
The transmitter accepts parallel data from a write to the transmitter holding register (UTHR). In FIFO
mode, the data is placed directly into an internal transmitter shift register of the transmitter FIFO. The
transmitter converts the data to a serial bit stream, inserting the appropriate START, STOP, and optional
parity bits. Finally, it outputs a composite serial data stream on the channel transmitter serial data output
signal (SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data bits on the channel receiver serial data input signal (SIN); converts it to
parallel format; checks for a START bit, parity (if any), and STOP bits; and transfers the assembled
character (with START, STOP, parity bits removed) from the receiver buffer (or FIFO) in response to a
read of the UART’s receiver buffer register (URBR). The receiver status may be polled or interrupt driven.