Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-7
Figure 4-2 shows a timing diagram of the hard reset flow.
Figure 4-2. Hard Reset Flow
4.3 Reset Configuration
The device is initialized using two complementary methods: latching CFG_RESET_SOURCE and
loading the reset configuration words. Initially, CFG_RESET_SOURCE is sampled during the assertion
of the PORESET signal. These signals determine whether a reset configuration word is required and the
device source interface from which it is loaded. According to the value on these signals, the device
continues loading the reset configuration word.
4.3.1 Reset Configuration Signals
Reset configuration input signals are on device pins that have other functions when the device is not in
reset state. These input signals are sampled into registers during the assertion of PORESET
, after a stable
clock is supplied (SYS_CLK_IN), and must be pulled high or low by external resistors as long as HRESET
is asserted. While the PORESET
or HRESET signal is asserted, all other signal drivers connected to these
signals must be in the high-impedance state. For proper resistor values for pulling reset configuration
signals high or low, see MPC8308 PowerQUICC II Pro Processor Hardware Specification.
This section describes the modes configured by the reset configuration signals. Note that the reset
configuration input sampled values are accessible to software through memory-mapped registers, as
PORESET
TRST
HRESET
Reset Configuration
Reset Configuration
(Input)
(Input or Output)
(Input)
Input Signals
Words Loading
End loading reset
configuration words.
Duration depends on
source
Start loading reset
configuration words
Stable clock
SYS_CLK_IN