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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-25
17.5.8.1 Slave Transmitter and Received Acknowledge
In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read of
I2CDR then releases SCL so that the master can generate a STOP condition. See Figure 17-11.
17.5.8.2 Loss of Arbitration and Forcing of Slave Mode
When a master loses arbitration the following conditions all occur:
• I2CSR[MAL] is set
• I2CCR[MSTA] is cleared (changing the master to slave mode)
• An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear it if it is
set. See Section 17.4.2.1, “Arbitration Control.”