Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-24 Freescale Semiconductor
During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to determine the
direction of the subsequent transfer and I2CCR[MTX] should be programmed accordingly. For
slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and I2CCR[MTX] must be read to
determine the direction of the current transfer (see Figure 17-11).
17.5.5 Generation of STOP
A data transfer ends with a STOP condition generated by the master device. A master transmitter can
generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CCR[TXAK]) before
reading the next-to-last byte of data. At this time, the next-to-last byte of data has been transferred on the
I
2
C interface, so the last byte does not receive the data acknowledge (because I2CCR[TXAK] is set).
Before the interrupt service routine reads the last byte of data, a STOP condition must first be generated.
17.5.6 Generation of Repeated START
At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START condition followed by another slave address without first generating a STOP condition. This is
accomplished by setting I2CCR[RSTA].
17.5.7 Generation of SCL When SDA is Negated
It is sometimes necessary to force the I
2
C module to become the I
2
C bus master out of reset and drive
SCLn (even though SDA may already be driven, which indicates that the bus is busy). This can occur when
a system reset does not cause all I
2
C devices to be reset. Thus, SDA can be negated low by another I
2
C
device while this I
2
C module is coming out of reset and will stay low indefinitely. The following procedure
can be used to force this I
2
C module to generate SCL so that the device driving SDA can finish its
transaction:
1. Disable the I
2
C module and set the master bit by setting I2CCR to 0x20.
2. Enable the I
2
C module by setting I2CCR to 0xA0.
3. Read I2CDR.
4. Return the I
2
C module to slave mode by setting I2CCR to 0x80.
17.5.8 Slave Mode Interrupt Service Routine
In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling
of its own address has been received. If I2CSR[MAAS] is set, software should set the transmit/receive
mode select bit (I2CCR[MTX]) according to the R/W command bit (I2CSR[SRW]). Writing to I2CCR
clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address
cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS.
A data transfer can then be initiated by writing to I2CDR for slave transmits or dummy reading from
I2CDR in slave-receive mode. The slave negates SCL between byte transfers. SCL is released when
I2CDR is accessed in the required mode.