Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-23
17.5.2 Initialization Sequence
A hard reset initializes all of the I
2
C registers to their default states. The following initialization sequence
initializes the I
2
C unit:
1. All I
2
C registers must be located in a cache-inhibited page.
2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the
CSB (platform) clock.
3. Update I2CADR to define the slave address for this device.
4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
disable.
5. Set the I2CCR[MEN] to enable the I
2
C interface.
17.5.3 Generation of START
After initialization, the following sequence can be used to generate START:
1. If the device is connected to a multimaster I
2
C system, check whether the serial bus is free
(I2CSR[MBB] = 0) before switching to master mode.
2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode (set
I2CCR[MTX]) for the address cycle.
3. Write the slave address being called into I2CDR. The data written to I2CDR[0–6] forms the slave
calling address. I2CCR[MTX] indicates the direction of transfer (transmit/receive) required from
the slave.
The scenario above assumes that the I
2
C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any time,
an I
2
C interrupt is generated (provided interrupt reporting is enabled with I2CCR[MIEN] =1).
17.5.4 Post-Transfer Software Response
Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]), which
indicates that one byte has been transferred. The I
2
C interrupt bit (I2CSR[MIF]) is also set and an interrupt
is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CCR[MIEN] is set). In the interrupt handler, software must take the following steps:
1. Clear I2CSR[MIF]
2. Read the I2CDR in receive mode or write to I2CDR in transmit mode. Note that this causes
I2CSR[MCF] to be cleared, as shown in Figure 17-11.
3. When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If
master receive mode is required, I2CCR[MTX] must be toggled at this stage (see Figure 17-11).
If the interrupt function is disabled, software can service the I2CDR in the main program by monitoring
I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF] because MCF behaves
differently when arbitration is lost. Note that interrupt or other bus conditions may be detected before the
I
2
C signals have time to settle. Thus, when polling I2CSR[MIF] (or any other I2CSR bits), software delays
may be needed to give the I
2
C signals sufficient time to settle.