Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-21
register and data that causes the setting of the required GPIO signal. The GPIO signal may be used for an
external device or for debug purposes.
17.5 Initialization/Application Information
This section describes some programming guidelines recommended for the I
2
C interface. Figure 17-11 is
a recommended flowchart for I
2
C interrupt service routines.
A sync assembly instruction must be executed after each I
2
C register read/write access to guarantee that
register accesses occur in order.
The I
2
C controller does not guarantee its recovery from all illegal I
2
C bus activity. In addition, a
malfunctioning device may hold the bus captive. A good programming practice is for software to rely on
a watchdog timer to help recover from I
2
C bus hangs. The recovery routine should also handle the case
when the illegal I
2
C bus behavior causes the status bits returned after an interrupt to be inconsistent with
what was expected.
17.5.1 Interrupt Service Routine Flowchart
Figure 17-11 shows an example algorithm for an I
2
C interrupt service routine. Deviation from the
flowchart may result in unpredictable I
2
C bus behavior. However, in the slave receive mode (not shown),
the interrupt service routine may need to set I2CCR[TXAK] when the next-to-last byte is to be accepted.