Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-6 Freescale Semiconductor
Figure 4-1 shows a timing diagram of the power-on reset flow.
Figure 4-1. Power-On Reset Flow
NOTE
It takes about 150 SYS_CLK_IN cycles between the negation of PORESET
and access to reset configuration word.
4.2.3 Hard Reset Flow
The HRESET signal is initiated externally by asserting HRESET or internally when the device detects a
reason to generate an internal hard reset sequence. In both cases, the device continues asserting HRESET
throughout the HRESET
state. The hard reset sequence time varies according to the configuration source
and SYS_CLK_IN frequency. The reset configuration input signal (CFG_RESET_SOURCE) is not
sampled by hard reset (only by power-on reset), so the device immediately starts loading the reset
configuration words and configures the device as explained in Section 4.3.3, “Loading the Reset
Configuration Words.” After the configuration sequence completes, the device releases the HRESET
signal and exits the HRESET state. An external pull-up resistor should negate the signals. After negation
is detected, a 16-cycle period is taken before testing for the presence of an external (hard) reset.
NOTE
Because the device does not sample the reset configuration input signals
(CFG_RESET_SOURCE) during a hard reset flow, setting a new value on
those signals (other than that set during power-on reset) has no effect.
TRST
HRESET
Reset Configuration
Reset Configuration
(Output)
(Input)
Input Signals
Words Loading
PLLs are
locked (no
external
indication)
Min. 32 SYS_CLK_IN
cycles
End loading reset
configuration words.
Duration depends on
source
Start loading reset
configuration words
Stable clock
SYS_CLK_IN
PORESET
(Input)