Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-16 Freescale Semiconductor
17.4.4.2.2 Filtering of SCL and SDA Lines
The SCL and SDA inputs are filtered to eliminate noise. Three consecutive samples of the SCL and SDA
lines are compared to a pre-determined sampling rate. If they are all high, the output of the filter is high.
If they are all low, the output is low. If they are any combination of highs and lows, the output is whatever
the value of the line was in the previous clock cycle.
The sampling rate is equal to a binary value stored in the frequency register I2CDFSRR. The duration of
the sampling cycle is controlled by a down counter. This allows a software write to the I2CDFSRR to
control the filtered sampling rate.
17.4.4.3 Clock Stretching
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master
has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave
SCL low period is greater than the master SCL low period, the resulting SCL low period is extended.
17.4.5 Boot Sequencer Mode
Boot sequencer mode is selected at power-on reset by the BOOTSEQ field of the high-order reset
configuration word. If boot sequencer mode is selected, the I
2
C module communicates with one or more
EEPROMs through the I
2
C interface. EEPROMs can be programmed to initialize one or more
configuration registers. Note that as described in Section 4.3.2.2.2, “Boot Sequencer Configuration,” the
default value for BOOTSEQ is 0b00, which corresponds to the I
2
C boot sequencer being disabled at
power-up.
Boot sequencer mode also supports an extension of the standard I
2
C interface that uses more address bits
to allow for EEPROM devices that have more than 256 bytes. This extended addressing mode is selectable
using a different encoding in the BOOTSEQ field of the high-order reset configuration word (see
Section 4.3.2.2.2, “Boot Sequencer Configuration.”) In this mode, only one EEPROM device can be used
and the maximum number of registers is limited by the size of the EEPROM.
If the standard I
2
C interface is used, the I
2
C module addresses the first EEPROM, and reads 256 bytes.
Then it issues a repeated start and addresses the next EEPROM address. This sequence continues until the
CONT bit is cleared. If the last register is not detected before wrapping back to the first address, an error
condition is detected. In other words, if the CONT bit for not cleared on the final 7 bytes, an error condition
is detected, causing the I
2
C controller to hang. The I
2
C module continues to read from the EEPROM as
long as the continue (CONT) bit is set in the EEPROM. The CONT bit resides in the address/attributes
field that is transferred from the EEPROM, as described in Section 17.4.5.2, “EEPROM Calling Address.”
There should be no other I
2
C traffic when the boot sequencer is active.
17.4.5.1 Using the Boot Sequencer for Reset Configuration
The reset configuration word can be loaded by using the I
2
C boot sequencer. See Section 4.3.2.2.2, “Boot
Sequencer Configuration.”